The present invention relates to an integrated circuit device having programmable junctions, and more particularly to a structure of and a method of designing programmable junctions of a field programmable gate array (FPGA) or a multimicroprocessor system.
FPGAs comprise a matrix of logic cells capable of performing various logic operations and a plurality of intercell signal lines disposed between the logic cells. The intercell signal lines are connectable to input/output terminals of the logic cells to connect the logic cells in an optional combination for thereby achieving a desired logic circuit. Therefore, junctions between the intercell signal lines and the input/output terminals of the logic cells have a programmable structure, i.e., comprise a set or cluster of program switches.
One simple approach to connecting the logic cells with greater flexibility is to provide as many program switches as possible. Consequently, conventional FPGAs have program switches so positioned at the junctions as to be able to connect all commutable input terminals of the logic cells freely to intercell signal lines. Alternatively, those program switches are positioned to substantially perform such a function.
An FPGA chip has an area of a matrix of logic cells, an area of intercell buses comprising a plurality of intercell signal lines, junctions comprising a plurality of program switches, and a switch block connecting horizontal and vertical intercell signal lines. The density of an FPGA logic circuit is substantially inversely proportional to the total number of program switches at the junctions and the area of each of the program switches for the reason that most of the area of the FPGA chip is occupied by the junctions having the program switches.
In order to increase the number of logic gates that can be realized per unit area so as to increase an area efficiency, it is necessary to reduce the total number of program switches thereby to reduce the area of the junctions.
However, since the program switches of the conventional FPGAs are so positioned as to be able to connect all the commutable input terminals of the logic cells freely to the intercell signal lines, the area efficiency of the resultant logic circuit tends to be low. This problem holds true for the junctions of a multimicroprocessor system in which microprocessors are connectable in an optional combination.